1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a vertical MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) having a trench structure.
2. Description of the Prior Art
Recent vertical MOSFETs that have attracted much attention have a trench structure which includes a gate electrode embedded in a trench. Known structures of a vertical MOSFET having a trench structure and methods of fabricating such a vertical MOSFET are disclosed in Japanese laid-open patent publication Nos. 4-146674 and 5-335582, for example.
The structure of a known vertical MOSFET having a trench structure will be described below with reference to FIG. 1 of the accompanying drawings. As shown in FIG. 1, the vertical MOSFET includes a semiconductor substrate having a p.sup.- channel layer 12 in its surface, an n.sup.- drain layer 11a underneath the p.sup.- channel layer 12, and an n.sup.+ drain layer 11b underneath the n.sup.- drain layer 11a. The semiconductor substrate has a number of trenches 13 defined in the p.sup.- channel layer 12 and extending vertically into the n.sup.- drain layer 11a. A gate oxide layer 14 is formed on the surface of each of the trenches 13, and a gate electrode 15 made of polycrystalline silicon or the like is embedded in each of the trenches 13. The vertical MOSFET also has a number of p.sup.+ body layers 17 disposed on the surface of the p.sup.- channel layer 12 at respective positions intermediate between adjacent ones of the trenches 13. N.sup.++ source layers 16 are disposed adjacent to the p.sup.+ body layers 17 and the trenches 13. Insulating layers 18 are disposed on the respective gate electrodes 15. A metal electrode 19 made of aluminum or the like is disposed over the entire surface of a cell region of the vertical MOSFET. The insulating layers 18 isolate the gate electrodes 15 and the metal electrode 19 from each other. The metal electrode 19 is held in ohmic contact with the n.sup.++ source layers 16 and the p.sup.+ body layers 17.
When a voltage equal to or higher than a predetermined threshold is applied to the gate electrodes 15 between the drain layers 11a, 11b and the n.sup.++ source layers 16, an n-type inverted layer is developed along the trenches in the p.sup.- channel layer 12, forming a current path thereby to turn on the region between the drain layers 11a, 11b and the n.sup.++ source layers 16. When the voltage applied to the gate electrodes 15 is reduced below the predetermined threshold, the n-type inverted layer developed in the p.sup.- channel layer 12 is eliminated, turning off the region between the drain layers 11a, 11b and the n.sup.++ source layers 16. Since the vertical current path is formed along the trenches 13 upon application of a voltage equal to or higher than the predetermined threshold, the current path has an area much greater than with a planar MOSFET, and hence the vertical MOSFET has a reduced resistance when it is turned on.
A process of manufacturing the conventional vertical MOSFET will be described below. First, a semiconductor substrate comprising an n.sup.+ drain layer 11b with an n.sup.- drain layer 11a disposed thereon is prepared. A p.sup.- channel layer 12 is formed in the surface of a cell region of the semiconductor substrate by ion implantation or the like. Then, p.sup.+ body layers 17 and n.sup.++ source layers 16 are formed by ion implantation or the like. Thereafter, trenches 13 extending from the channel layer 12 into the drain layer 11a are formed substantially centrally in the respective n.sup.++ source layers 16.
Gate oxide layers 14 are formed respectively in the trenches 13. A polycrystalline silicon film is deposited on the entire surface formed so far, and etched back to produce gate electrodes 15 embedded in the respective trenches 13. The entire surface is then covered with an insulating film, and apertures are formed in the insulating film above the source layers 16 and the body layers 17 by photolithography, leaving insulating films 18 respectively on the gate electrodes 15. A metal film such as a film of aluminum or the like is deposited on the entire surface, and processed by photolithography to form a metal electrode 19 on the entire surface of the cell region. The reverse surface of the n.sup.+ drain layer 11b is formed with a metal back electrode. In this manner, a principal structure of the vertical MOSFET is completed.
The above process of manufacturing the conventional vertical MOSFET suffers the following problems: First, various heat treatment steps are required. For example, a heat treatment step for sacrifice oxidization is needed to form and remove an oxide layer for processing crystal defects, etc. caused due to the formation of the trenches 13 subsequent to the formation of the n.sup.++ source layers 16. Other heat treatment steps include a heat treatment step for forming the gate oxide layers 14 and a heat treatment step for forming the gate electrodes 15 by CVD or the like. These heat treatment steps are responsible for causing the n.sup.++ source layers 16 to be diffused again, developing a short channel between them and the drain layer 11a with a resulting increase in current leakage between the source and drain.
Secondly, since the trenches 13 are formed after the n.sup.++ source layers 16 are formed and the gate electrodes 15 are embedded in the trenches 13 by etchback, when the gate electrodes 15 of polycrystalline silicon are etched back to a large depth with respect to the diffused depth of the source layers 16, the upper ends of the gate electrodes 15 tend to be separated from the lower ends of the source layers 16, with no overlapping region left between gate electrodes 16 and the source layers 15. As a consequence, the vertical MOSFET has a higher threshold, and suffers a reduced yield.